Multiprocessing systems continue to become increasingly important in computing systems for many applications, including general purpose processing systems and embedded control systems. In the design of such multiprocessing systems, an important architectural consideration is scalability. In other words, as more hardware resources are added to a particular implementation the machine should produce higher performance. Not only do embedded implementations require increased processing power, many also require the seemingly contradictory attribute of providing low power consumption. In the context of these requirements, particularly for the embedded market, solutions are implemented as “Systems on Chip” or “SoC.” The assignee of the present application, MIPS Technologies, Inc., offers a broad range of solutions for such SoC multiprocessing systems.
In multiprocessing systems, loss in scaling efficiency may be attributed to many different issues, including long memory latencies and waits due to synchronization. The present invention addresses improvements to synchronization among threads in a multithreaded multiprocessing environment, particularly when individual threads may be active on one or more multiple processors, on a single processor but distributed among multiple thread contexts, or resident in memory (virtualized threads).
Synchronization in a multithreaded system refers to the activities and functions of such a multiplicity of threads that coordinate use of shared system resources (e.g., system memory and interface FIFOs) through variables storing “state” bits for producer/consumer communication and mutual exclusion (MUTEX) tasks. Important considerations for implementing any particular synchronization paradigm include designing and implementing structures and processes that provide for deadlock-free operation while being very efficient in terms of time, system resources, and other performance measurements.
Details regarding the MIPS processor architecture are provided in the following document, which is incorporated by reference in its entirety for all purposes: D. Sweetman, See MIPS Run, Morgan Kaufmann Publishers, Inc. (1999).
The difficulty of finding a hardware synchronization solution for a RISC processor is compounded by the nature of the RISC paradigm. A CISC paradigm is easier, in some ways, to adapt hardware resources to particular problems because the instruction set may be extended virtually without limit as instructions and operands in an instruction pipeline may be of variable length. A designer that wants to implement a special hardware synchronization instruction set is able to add new synchronization instructions easily as many CISC instruction sets already contemplate extensions to basic instruction sets. However, that solution is generally not available to designers working with RISC instruction sets. Most instructions sets are filled or nearly filled with vacancies judiciously filled after many factors are extensively considered and evaluated. What is needed is a system for extending or enhancing existing instruction sets, with such a solution particularly useful in the RISC environment, but not exclusively useful as the CISC environment may also benefit from instruction set extension.